1. Field of the Invention
The present invention relates to an imaging apparatus and an imaging system.
2. Description of the Related Art
A pixel unit where a selection transistor is excluded and a plurality of photoelectric conversion units share a reset transistor and an amplification transistor has been proposed for reducing a pixel area in an imaging apparatus such as a CMOS image sensor, as disclosed in Japanese Patent Laid-Open No. 2004-172950.
In the technique disclosed in Japanese Patent Laid-Open No. 2004-172950, a global selection signal line is set to a low electric potential, and the reset transistors of all pixel units are turned on every time a signal is read out, thereby deselecting all pixel units. Then, the global selection signal line is set to a high electric potential, and the reset transistors of selected pixel units are turned on, thereby selecting only the selected pixel units. That is, it is necessary to frequently switch the electric potential of the global selection signal line. The global selection signal line is connected to all pixel units. For this reason, when the number of pixel units increases, the parasitic capacitance of the line increases, and the charge/discharge time becomes long. Hence, a long time is required to switch the electric potential in reading out a signal from a pixel unit. It is therefore difficult to read out a signal from a pixel unit at a high speed.